Semiconductor memory apparatus and method for reading data from the same

ABSTRACT

A semiconductor memory apparatus includes a memory block including memory cells coupled between a bit line and a source line and operating in response to voltages applied to word lines, and a peripheral circuit suitable for performing operations relating to data input and output of the memory cells, wherein the peripheral circuit is suitable for applying a precharge voltage to the bit line when word lines adjacent to a selected word line are set to a floating state.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a Division of U.S. application Ser. No.14/189,240, filed on Feb. 25, 2014, and the present application claimspriority to Korean patent application number 10-2013-0112722 filed onSep. 23, 2013, in the Korean Intellectual Property Office, the entiredisclosure of which is incorporated by reference herein.

BACKGROUND

1. Technical Field

Various embodiments relate generally to a semiconductor memory apparatusand, more particularly, to a semiconductor memory apparatus including amemory cell coupled to a word line.

2. Related Art

A sufficient amount of current is to be ensured in order to improveinput and output operating characteristics of memory cells. However,operating characteristics may be deteriorated due to changes in thestructure of a memory block or a reduction in size of memory cells.

BRIEF SUMMARY

Various embodiments relate to a semiconductor memory apparatus capableof improving operating characteristics.

A semiconductor memory apparatus according to an embodiment of thepresent invention may include a memory block including memory cellscoupled between a bit line and a source line and operating in responseto voltages applied to word lines, and a peripheral circuit suitable forperforming operations relating to data input and output of the memorycells, wherein the peripheral circuit is suitable for applying aprecharge voltage to the bit line when word lines adjacent to a selectedword line are set to a floating state.

A semiconductor memory apparatus according to an embodiment of thepresent invention may include a memory block including memory cellscoupled between a bit line and a source line and operating in responseto voltages applied to word lines, and a peripheral circuit suitable forperforming operations related to data input and output of the memorycells, wherein the peripheral circuit is suitable for applying a passvoltage to a word line adjacent to a selected word line in a directionof the bit line and subsequently applying a precharge voltage to the bitline when the word line adjacent to the selected word line is set to thefloating state.

A semiconductor memory apparatus according to an embodiment of thepresent invention may include a memory block including memory cellsoperating in response to voltages applied to word lines and selectiontransistors operating in response to voltages applied to selection linesbetween a bit line and a source line, and a peripheral circuit suitablefor performing operations related to data input and output of the memorycells, wherein the peripheral circuit is suitable for turning on theselection transistors when a pass voltage is applied to unselected wordlines and turning off and subsequently turning on the selectiontransistors when the precharge voltage is applied to the bit line andthe unselected word lines are set to a floating state.

A memory system according to an embodiment may include: a non-volatilememory apparatus; and a memory controller configured for controlling thenon-volatile memory apparatus, wherein the non-volatile memory apparatusincludes: a memory block including memory cells coupled between a bitline and a source line and operating in response to voltages applied toword lines; and a peripheral circuit suitable for performing operationsrelating to data input and output of the memory cells, wherein theperipheral circuit is suitable for applying a precharge voltage to thebit line when word lines adjacent to a selected word line are set to afloating state.

A OneNand flash memory apparatus according to an embodiment may include:a NAND flash cell array; and a controller configured to perform read andwrite operations in response to a control signal received externallyfrom the controller, wherein the NAND flash cell array includes: amemory block including memory cells coupled between a bit line and asource line and operating in response to voltages applied to word lines;and a peripheral circuit suitable for performing operations relating todata input and output of the memory cells, wherein the peripheralcircuit is suitable for applying a precharge voltage to the bit linewhen word lines adjacent to a selected word line are set to a floatingstate.

A computing system according to an embodiment may include a memorysystem and a central processing unit, the memory system including: asemiconductor memory apparatus; and a memory controller configured tocontrol the semiconductor memory apparatus, wherein the semiconductormemory apparatus includes: a memory block including memory cells coupledbetween a bit line and a source line and operating in response tovoltages applied to word lines; and a peripheral circuit suitable forperforming operations relating to data input and output of the memorycells, wherein the peripheral circuit is suitable for applying aprecharge voltage to the bit line when word lines adjacent to a selectedword line are set to a floating state.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a semiconductor memory apparatusaccording to an embodiment of the present invention;

FIGS. 2A and 2B are circuit diagrams illustrating embodiments of memoryblocks shown in FIG. 1;

FIG. 3 is a view illustrating a current flow through a memory cellaccording to an embodiment of the present invention;

FIGS. 4A to 4E are views illustrating a current flow through a memorystring including a memory cell transistor shown in FIG. 3;

FIGS. 5A to 5G are views illustrating operations of a semiconductormemory apparatus according to embodiments of the present invention;

FIG. 6 is a schematic block diagram illustrating a memory systemaccording to an embodiment of the present invention;

FIG. 7 is a schematic block diagram illustrating a fusion memoryapparatus or a fusion memory system according to the aforementionedvarious embodiments; and

FIG. 8 is a schematic block diagram illustrating a computing systemincluding a flash memory apparatus according to an embodiment of thepresent invention.

DETAILED DESCRIPTION

Hereinafter, various embodiments will be described in detail withreference to the accompanying drawings. The figures are provided toallow those having ordinary skill in the art to understand the scope ofthe embodiments of the disclosure. The present invention may, however,be embodied in different forms and should not be construed as limited tothe embodiments set forth herein. Rather, these embodiments are providedso that this disclosure will be thorough and complete, and will fullyconvey the scope of the present invention to those skilled in the art.

Furthermore, ‘connected/coupled’ represents that one component isdirectly coupled to another component or indirectly coupled throughanother component. In this specification, a singular form may include aplural form as long as it is not specifically mentioned in a sentence.Furthermore, ‘include/comprise’ or ‘including/comprising’ used in thespecification represents that one or more components, steps, operations,and elements exists or are added. Additionally, wherever possible, thesame reference numbers will be used throughout the drawings to refer tothe same or like parts unless otherwise noted.

FIG. 1 is a block diagram illustrating a semiconductor memory apparatusaccording to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor memory apparatus may include amemory array 110 and peripheral circuits 120 to 160.

The memory array 110 may include a plurality of memory blocks 110MB. Theconfiguration of the memory blocks 110MB is described below.

FIGS. 2A and 2B are circuit diagrams illustrating embodiments of thememory blocks shown in FIG. 1.

Referring to FIG. 2A, each of the memory blocks 110MB may include aplurality of memory strings ST that are coupled between bit lines BL0 toBLk and a common source line CSL. In other words, each of the memorystrings ST may correspond to each of the bit lines BL0 to BLk, and thememory strings ST may be coupled in common to the common source lineCSL. Each of the memory strings ST may include a source selectiontransistor SST having a source coupled to the common source line CSL, acell string to which the memory cells C00 to Cn0 are coupled in series,and a drain selection transistor DST having a drain coupled to the bitline BL0. The memory cells C00 to Cn0, included in the cell string, maybe coupled in series between the source and drain selection transistorsSST and DST. A gate of the source selection transistor SST may becoupled to a source selection line SSL, gates of the memory cells C00 toCn0 may be coupled to word lines WL0 to WLn, respectively, and a gate ofthe drain selection transistor DST may be coupled to the drain selectionline DSL.

The drain selection transistor DST may control connection ordisconnection between the cell strings C00 to Cn0 and the bit lines, andthe source selection transistor SST may control connection ordisconnection between the cell strings C00 to Cn0 and the common sourceline CSL.

In a NAND flash memory, memory cells included in a memory cell block maybe divided into physical pages or logical pages. For example, the memorycells C00 to C0 k coupled to a single word line, e.g., the word line WL0may form a single physical page PAGE. In addition, even-numbered memorycells C00, C01, C03, C05 and C0 k, coupled to the word line WL0, mayform a single even physical page, and odd-numbered memory cells C00,C02, C04 and C0 k−1 may form a single odd physical page. These pages (oreven and odd pages) may be a basic unit for a program operation or aread operation.

Referring to FIG. 2B, when the memory blocks 110MB have athree-dimensional structure, each of the memory blocks 110MB may includethe memory strings ST. For example, in a P—BiCS structure, each of thememory strings ST may include a first memory string MT1 and a secondmemory string MT2. The first memory string MT1 may be coupled in avertical direction between the common source line CSL and a pipetransistor Pta of a substrate. The second memory string MT2 may becoupled between the bit line BL and the pipe transistor Pta of thesubstrate. The first memory string MT1 may include the source selectiontransistor SST and memory cells C0 to C7. The source selectiontransistor SST may be controlled by a voltage applied to a sourceselection line SSLa1, and the memory cells C0 to C7 may be controlled byvoltages applied to the stacked word lines WLa0 to WLa7. The secondmemory string MT2 may include the drain selection transistor DST andmemory cells C8 to C15. The drain selection transistor DST may becontrolled by a voltage applied to a drain selection line DSLa1, and thememory cells C8 to C15 may be controlled by voltages applied to thestacked word lines WLa8 to WLa15.

When the memory block 110MB is selected, the pipe transistor Pta, whichis coupled between a pair of the memory cells C7 and C8 located in themiddle of the memory string of the P—BiCS structure, may electricallyconnect channel layers of the first memory string MT1, included in theselected memory block 110MB, and channel layers of the second memorystring MT2.

In a memory block having a two-dimensional structure, a single memorystring may be coupled to each bit line, and drain selection transistorsof the memory block may be simultaneously controlled by a single drainselection line. However, in the memory block 110MB having a 3Dstructure, the memory strings ST may be coupled in common to each bitline BL. The number of memory string ST that are coupled in common tothe single line BL and controlled by the same word lines within the samememory block 110MB may vary according to different design needs.

Since the plurality of memory strings are coupled in parallel with thesingle bit line BL, the drain selection transistors DST may beindependently controlled by selection voltages applied to drainselection lines DSLa1 to DSLa4 in order to selectively couple the singlebit line BL to the memory strings ST.

The memory cells C0 to C7 of the first memory string MT1 and the memorycells C8 to C15 of the second memory string MT2, which are coupled inthe vertical direction in the memory block 110MB, may be individuallycontrolled by operating voltages applied to stacked word lines WLa0 toWLa7 and stacked word lines WLa8 to WLa15. These word lines WLa0 toWLa15 may be divided into memory block units. In FIG. 2B, word linesWLb0 to WLb15, drain selection lines DSLb1 to DSLb4, source selectionline SSLa1 to SSLa4, SSLb1 to SSLb4, and pipe gates PG1 and PG2 are alsoillustrated.

Referring again to FIGS. 1 and 2A, the peripheral circuits 120 to 160may be suitable for performing a program loop, an erase loop and a readoperation on the memory cells C00 to C0 k coupled to a selected wordline, e.g., the word line WL0. The peripheral circuits 120 to 160 may besuitable for performing a program loop, an erase loop and a readoperation in response to control of the control circuit 120. In order toperform the program loop, the erase loop and the read operation, theperipheral circuits 120 to 160 may be suitable for selectivelyoutputting operating voltages Verase, Vpgm, Vread, Vpass, Vdsl, Vssl andVsl to local lines SSL, WL0 to WLn and DSL and the common source lineCSL of the selected memory block, controlling a precharge or dischargeoperation of the bit lines BL0 to BLk, or sensing a current flow throughthe bit lines BL0 to BLk.

In a NAND flash memory, an operation circuit may include a controlcircuit 120, a voltage supply circuit 130, a read/write circuit 150, acolumn selection circuit 160 and an input/output circuit 170. Eachcomponent is described below.

The control circuit 120 may output a voltage control signal CMD_bias inresponse to a command signal CMD, which is input from exterior throughthe input/output circuit 170, in order to control the voltage supplycircuit 130 so that the operating voltages Verase, Vpgm, Vread, Vpass,Vdsl, Vssl and Vsl may be generated at desired levels to perform aprogram loop, an erase loop and a read operation. In addition, thecontrol circuit 120 may output control signals CMD_rw for controllingthe read/write circuit 150 in order to perform the program loop, theerase loop and the read operation. In addition, when an address signalADD is input to the control circuit 120, the control circuit 120 mayoutput a column address signal CADD and a row address signal RADD. Therow address RADD may be output to the voltage supply circuit 130, andthe column address CADD may be output to the column selection circuit160.

The voltage supply circuit 130 may generate the operating voltagesVerase, Vpgm, Vread, Vpass, Vdsl, Vssl and Vsl used to perform theprogram loop, the erase loop and the read operation on memory cells inresponse to the voltage control signal CMD_bias of the control circuit120. The voltage supply circuit 130 may output the operating voltages tothe common source line CSL and the local lines SSL, WL0 to WLn and DSLof the selected memory block in response to the row address signal RADDfrom the control circuit 120.

The voltage supply circuit 130 may include a voltage generator 131 and arow decoder 133. The voltage generator 131 may generate the operatingvoltages Verase, Vpgm, Vread, Vpass, Vdsl, Vssl and Vsl in response tothe voltage control signal CMD_bias of the control circuit 120. The rowdecoder 133 may transfer the operating voltages to the common sourceline CSL and the local lines SSL, WL0 to WLn and DSL of the selectedmemory block, among the memory blocks 110MB, in response to the rowaddress signal RADD from the control circuit 120.

As described above, the voltage supply circuit 130 may output and changethe operating voltages Verase, Vpgm, Vread, Vpass, Vdsl, Vssl and Vsl tobe described below in response to the voltage control signal CMD_biasfrom the control circuit 120.

The read/write circuit 150 may be coupled to the memory blocks 110MB ofthe memory array 110 through the bit lines BL0 to BLk. The read/writecircuit 150 may selectively precharge the bit lines BL0 to BLk inresponse to the control signal CMD_rw from the control circuit 120 andthe data DATA to be stored in the memory cells during a programoperation. During a program verify operation or a read operation, theread/write circuit 150 may precharge the bit lines BL0 to BLk, sensechanges in voltage or current of the bit lines BL0 to BLk and latchdata, read from the memory cells, in response to the control signalCMD_rw from the control circuit 120.

The column selection circuit 160 may sequentially transfer the data fromthe input/output circuit 170 to the read/write circuit 150 or maysequentially transfer the data, latched to the read/write circuit 150,to the input/output circuit 170 in response to the column address CADDoutput from the control circuit 120.

The input/output circuit 170 may transfer the command signal CMD and theaddress signal ADD, which are externally input, to the control circuit120. In addition, the input/output circuit 170 may transfer theexternally input data DATA to the column selection circuit 160 during aprogram operation or may externally output the data, read from thememory cells, during a read operation.

FIG. 3 is a view illustrating a current flow through a memory cellaccording to an embodiment of the present invention.

Referring to FIG. 3, when a gate voltage VG is applied to a gate of amemory cell transistor having a channel length L and a threshold voltageVT, and a drain voltage VBL is applied to a drain thereof, a current Iflowing through the memory cell transistor may be expressed by theproduct of an electric charge Q, induced on a channel of the memory celltransistor, and a carrier velocity v. In order to improve data input andoutput characteristics, an operating current I of the memory celltransistor is to be increased.

The electric charge Q induced on the channel of the memory celltransistor may be in proportion to VG-VT-Vch, where Vch may be a channelelectric potential, Vch at a source side may be 0V, and Vch at a drainside may be VBL. Therefore, the cell current I will be reduced after thememory cell transistor is programmed to increase the threshold voltageVT and the same gate voltage VG is subsequently applied.

The carrier velocity v may depend on an electric field (e.g., E=VBL/L)that is applied to the channel of the memory cell transistor. When theelectric field is low, the carrier velocity v may be in proportion tothe electric field. However, the carrier velocity may be saturated at anelectric field of a predetermined intensity or more. A memory celltransistor, reduced in size to achieve a high degree of integration, hasalready been operating in a short channel region. After the memory celltransistor is programmed, an effective gate voltage (VG,eff=VG−VT) maybe reduced. Thus, shortly after the drain voltage VBL is increased,pinch-off may occur. As a result, the carrier velocity v may besaturated.

Therefore, the operating current I of the memory cell transistor may beincreased by preventing saturation of a carrier velocity that may occurin an unselected word line and increasing the amount of the inducedelectric charge Q by ensuring the effective gate voltage (VG,eff=VG−VT)in the unselected word line.

FIGS. 4A to 4E are views illustrating a cell current in a memory stringincluding the memory cell transistor shown in FIG. 3.

Referring to FIG. 4A, the x-axis represents positions of transistorsincluded in a memory string, and the y-axis represents an electricpotential at each position. In the memory string, a pass voltageVpass_read may be applied to an unselected word line, and a read voltageVread may be applied to a selected word line Sel. WL. A description willbe made in reference to an example in which all memory cells areprogrammed to the highest program level (e.g., PV3), among programlevels (e.g., PV1 to PV3). In this example, a threshold voltage of amemory cell may have the highest voltage level (VT, PV3).

Under the above-described conditions, when a predetermined voltage(Vread) is applied to a selected word line in order to perform a readoperation (or verify operation), a channel under the selected word linemay pinch off. As a result, carrier velocity saturation may occur.Therefore, the operating current I may be ensured by increasing theelectric charge Q being induced on the channel. However, since a voltage(Vpass_read) that is applied to unselected word lines is fixed, theinduced electric charge Q may decrease as the drain voltage VBLincreases.

Referring to FIG. 4B, as the drain voltage VBL is further increased,carrier velocity saturation may also occur in a channel of theunselected word line. As a result, the induced electric charge Q may befurther reduced.

Referring to FIGS. 4C and 4D, the electric charge Q induced on thechannel may be ensured by changing a voltage applied to an unselectedword line according to a channel potential profile Vch(x). When anelectric potential of the unselected word line changes according to thechannel potential profile, the electric charge Q may be maintained whenthe drain voltage VBL is high (see FIG. 4D) as well as when the drainvoltage VBL is low (see FIG. 4C).

However, the electric potential of the unselected word line may have tobe controlled according to the channel potential profile Vch(x).

Therefore, when the drain voltage VBL having a high voltage level isapplied while the electric potential of the unselected word line iscontrolled according to the channel potential profile Vch (x), a largeelectric field may occur in unselected word lines Unsel.WL adjacent to aselected word line Sel.WL. As a result, hot carriers may be generated.

Therefore, as illustrated in FIG. 4E, injection of the hot carriers intomemory cells of the unselected word lines Unsel.WL, which is adjacent toa memory cell of the selected word line Sel.WL, may be prevented bycontrolling voltages applied to the unselected word lines Unsel.WL inorder to reduce an electric field in the corresponding region.

Hereinafter, embodiments of the present invention in which the voltagesapplied to the unselected word lines may be changed according to thechannel potential profile Vch(x) are described.

FIGS. 5A to 5F are views illustrating operations of a semiconductormemory apparatus according to embodiments of the present invention.

Referring to FIG. 5A, peripheral circuits (120 to 160 in FIG. 1) may besuitable for applying a precharge voltage VBL to the bit line BL whenthe unselected word lines Unsel.WL, adjacent to the selected word lineSEL.WL, are set to a floating state. This operation is described belowin detail.

First, during a gate bias setup period, a positive voltage may beapplied to the drain selection line DSL so that the drain selectiontransistor between the bit line BL and a memory cell may be turned on.In addition, the pass voltage VPASS_READ may be applied to the wordlines Sel.WL and Unsel.WL. In other words, the peripheral circuits 120to 160, shown in FIG. 1, may turn on the drain selection transistorcoupled between the bit line BL and the memory cell when the passvoltage VPASS_READ is applied to the word lines Sel.WL and Unsel.WL. Asa result, the word lines Sel.WL and Unsel.WL may be precharged by thepass voltage VPASS_READ. In addition, all memory cells in the memorystring may be turned on by the pass voltage VPASS_READ, and channelregions of the memory cells may be electrically connected to the bitline BL.

During a sensing bias setup period, the precharge voltage VBL may beapplied to the bit line BL, and the read voltage VREAD may be applied tothe selected word line Sel.WL. The peripheral circuits 120 to 160, shownin FIG. 1, may apply the precharge voltage VBL to the bit line BL whenor after the unselected word lines Unsel.WL, adjacent to the selectedword line Sel.WL, are floated. The peripheral circuits 120 to 160, shownin FIG. 1, may float the drain selection line DSL as well as theunselected word lines Unsel.WL.

As described above, when the precharge voltage VBL is applied to the bitline BL while the unselected word lines Unsel.WL are floated, thechannel potential profile Vch(x) may be formed, and the electricpotential of the unselected word lines Unsel.WL, floated by thecapacitor coupling phenomenon, may be changed according to thecorresponding channel potential profile Vch(x).

Therefore, since the voltage difference between the word line and thechannel, set during the gate bias setup period, is maintained, thechannel induced charge may not be changed. As a result, the operatingcurrent of the memory cell transistor may be stably ensured, and datainput and output characteristics may not be improved.

Thereafter, during a sensing period, the peripheral circuits 120 to 160,shown in FIG. 1, may apply the positive voltage to the source selectionline SSL so that the source selection transistor, coupled between thememory cell and the common source line CSL, may be turned on. Inaddition, the peripheral circuits may sense changes in voltage (orcurrent amount) of the bit line BL, latch data stored in memory cellsand output the latched data.

The peripheral circuits may apply the read voltage VREAD or the verifyvoltage to the selected word line Sel.WL when or after the prechargevoltage VBL is applied to the bit line BL. In addition, the peripheralcircuits may apply the read voltage VREAD or a verify voltage to theselected word line Sel.WL when or after the unselected word linesUnsel.WL adjacent to the selected word line Sel. WL are floated.

The time at which the bit line voltage VBL, the pass voltage VPASS_READand the read voltage VREAD are applied or the time at which the positivevoltage is applied to the selection lines DSL and SSL may be applied toembodiments to be described below.

As described above, the same pass voltage VPASS_READ may be applied toall unselected word lines Unsel.WL. However, an operating method ofapplying different pass voltages varying depending on positions of theunselected word lines Unsel.WL is illustrated with reference to in FIGS.5B to 5F.

There may be, at least, two main reasons for this operating method.

First, when the read voltage VREAD is applied to output informationstored in the selected word line Sel.WL, the electric potential of theunselected word lines Unsel.WL, which are in a floating state, may bechanged by the read voltage VREAD of the selected word line Sel.WL aswell as the channel potential profile Vch(x) due to a capacitor couplingphenomenon.

Since the read voltage VREAD is generally less than the pass voltageVPASS_READ, the electric potential of the unselected word linesUnsel.WL, which is reduced by the read voltage VREAD, may have to bereduced.

Second, referring to the channel potential profile, V_ch(x), asillustrated in FIGS. 4D and 4E, by floating the unselected word linesUnsel.WL, a strong electric field may be generated in a lower channel ofthe selected word line Sel.WL and the unselected word lines Unsel.WLadjacent thereto. Since hot carriers, generated by the strong electricfield, are likely to be injected into the memory cells of the selectedword line Sel.WL and the unselected word lines Unsel.WL adjacentthereto, the electric field may be appropriately controlled bycontrolling the electric potential of the unselected word linesUnsel.WL.

Referring to FIG. 5B, before unselected word lines Unsel.WL1 andUnsel.WL2 are set to a floating state, the peripheral circuits 120 to160, shown in FIG. 1, may apply a first pass voltage VPASS_READ1 to theunselected word lines Unsel.WL1 not adjacent to the selected word lineSel.WL and apply a second pass voltage VPASS_READ2 to the unselectedword lines Unsel.WL2 adjacent to the selected word line Sel.WL during agate bias setup period.

The second pass voltage VPASS_READ2 may vary and be input in response tothe read voltage VREAD.

In general, the second pass voltage VPASS_READ2 satisfyingVPASS_READ1+alpha*(VPASS_READ1−VREAD)±beta may be input in considerationof capacitor coupling with the selected word line Sel.WL, in which alphamay be controlled between 0 to 1.0 and may also be adjusted by beta inorder to prevent hot carrier generation.

As described above, the same pass voltage VPASS_READ2 may be applied tothe unselected word lines Unsel.WL2 adjacent to the selected word lineSel.WL. However, different pass voltages may be applied, depending onthe positions of the unselected word lines Unsel.WL1.

Referring to the channel potential profile V_ch(x) in the selected wordline Sel.WL, as illustrated in FIGS. 4D and 4E, the unselected word lineUnsel.WL adjacent to the selected word line Sel.WL in the direction ofthe common source line CSL and the unselected word line Unsel.WLadjacent thereto in a direction of the bit line BL may have differentchannel potentials. Therefore, the electric potentials of the unselectedword lines Unsel.WL adjacent thereto may be compensated.

Referring to FIG. 5C, before unselected word lines Unsel.WL1 toUnsel.WL3 are set to a floating state, the peripheral circuits 120 to160, shown in FIG. 1, may apply the first pass voltage VPASS_READ1 tothe unselected word lines Unsel.WL1, not adjacent to the selected wordline Sel.WL, the second pass voltage VPASS_READ2 to the unselected wordlines Unsel.WL2 adjacent thereto in the direction of the bit line BL anda third pass voltage VPASS_READ3 to the unselected word lines Unsel.WL3adjacent thereto in the direction of the common source line CSL during agate bias setup period.

The second pass voltage VPASS_READ2 applied to the unselected word linesUnsel.WL2 in the direction of the bit line BL may be changed and inputin response to the read voltage VREAD and the bit line bias VBL.

Generally, the second pass voltage VPASS_READ2 satisfyingVPASS_READ1+alpha*(VPASS_READ1−VREAD)±beta+gamma*VBL may be input inconsideration of capacitor coupling between the selected word lineSel.WL and the channel, where alpha may be controlled between 0 to 1.0and may also be adjusted by beta to avoid hot carrier generation, andgamma may be an experience constant and be controlled between −0.5 and0.5.

The third pass voltage VPASS_READ3 may be changed and input in responseto the read voltage VREAD.

Generally, the third pass voltage VPASS_READ3 satisfyingVPASS_READ1+alpha (VPASS_READ1−VREAD)±beta may be input in considerationof capacitor coupling with the selected word line Sel.WL, where alphamay be controlled between 0 to 1.0 and may also be adjusted to avoid hotcarrier generation.

As described above, the same pass voltage VPASS_READ1 may be applied tothe unselected word lines Unsel.WL1 not adjacent to the selected wordline Sel.WL. However, different pass voltages may be applied, dependingon the positions of the unselected word lines Unsel.WL1 not adjacent tothe selected word line Sel.WL.

Referring to the channel potential profile Vch(x) in the selected wordline Sel.WL, shown in FIGS. 4D and 4E, the unselected word line Unsel.WLnot adjacent thereto in the direction of the common source line CSL mayhave a lower channel potential than the unselected word line Unsel.WLnot adjacent thereto in the direction of the bit line BL.

Therefore, different pass voltages may be applied, depending on theunselected word lines Unsel.WL1, in order to reduce read disturb in theunselected word line Unsel.WL, not adjacent to the selected word lineSel.WL, caused by the pass voltage VPASS_READ.

Referring to FIG. 5D, before unselected word lines Unsel.WL1 toUnsel.WL4 are set to the floating state, the peripheral circuits 120 to160, shown in FIG. 1, may apply the first pass voltage VPASS_READ1 tothe unselected word lines Unsel.WL1, not adjacent to the selected wordline Sel.WL in the direction of the bit line BL, the second pass voltageVPASS_READ2 to the unselected word lines Unsel.WL2 adjacent thereto inthe direction of the bit line BL, the third pass voltage VPASS_READ3 tothe unselected word lines Unsel.WL3 adjacent thereto in the direction ofthe common source line CSL and a fourth pass voltage VPASS_READ4 to theunselected word lines Unsel.WL4 in the direction of the common sourceline CSL during a gate bias setup period.

The fourth pass voltage VPASS_READ4, applied to the unselected word lineUnsel.WL, not adjacent thereto in the direction of the common sourceline CSL, may be changed and input in response to the bit line bias VBL.

In general, the fourth pass voltage VPASS_READ4 satisfyingVPASS_READ1+gamma*VBL may be input in consideration of capacitorcoupling between the selected word line Sel.WL and the channel, andgamma may have a value between −1.0 and 0.

As described above, each of the unselected word lines Unsel.WL1 andUnsel.WL4, not adjacent to the selected word line Sel.WL, may be set tothe floating state. However, the unselected word lines Unsel.WL1 andUnsel.WL4, not adjacent to the selected word line Sel.WL, may be set toa floating state, depending on the positions thereof.

Referring to the channel potential profile Vch(x), shown in FIGS. 4D and4E, a voltage drop may mostly occur in the selected word line Sel.WL,and the unselected word line Unsel.WL4 not adjacent in the direction ofthe common source line CSL may approximate a source voltage (generally,0V).

Therefore, a voltage may continue to be applied to the unselected wordline Unsel.WL4 not adjacent thereto in the direction of the commonsource line CSL.

The fourth pass voltage VPASS_READ4, applied to the unselected word lineUnsel.WL4 not adjacent thereto in the direction of the common sourceline CSL, may be changed and continue to be input in response to the bitline bias VBL.

In general, the VPASS_READ4 satisfying VPASS_READ1+gamma*VBL may beinput, where gamma may have a value ranging between −1.0 and +1.0.

Referring to FIG. 5E, a gate bias setup period may be set as shown inFIG. 5D. During the sensing bias setup period, the peripheral circuits120 to 160, shown in FIG. 1, may set the selected word line Sel.WL andthe unselected word lines Unsel.WL1 not adjacent thereto in thedirection of the bit line BL, the unselected word lines Unsel.WL2adjacent thereto in the direction of the bit line BL and the unselectedword lines Unsel.WL3 adjacent thereto in the direction of the commonsource line CSL to the floating state, and the peripheral circuits 120to 160 may continue to apply the fourth pass voltage VPASS_READ4 to theunselected word lines Unsel.WL4 in the direction of the common sourceline CSL.

As described above, both the selected word line Sel.WL and theunselected word lines Unsel.WL2 and Unsel.WL3 adjacent thereto may beset to the floating state. However, the unselected word lines Unsel.WL2and Unsel.WL3 may be selectively set to the floating state, depending onthe positions of the selected word line Sel.WL and the unselected wordlines Unsel.WL2 and Unsel.WL3 adjacent thereto.

Referring to the channel potential profile Vch(x), shown in FIGS. 4D and4E, a voltage drop may mostly occur in the selected word line Sel.WL,and the unselected word lines Unsel.WL4 not adjacent thereto in thedirection of the common source line CSL and the unselected word lineUnsel.WL3 adjacent thereto in the direction of the common source lineCSL may approximate a source voltage (generally, 0V).

Therefore, a voltage may also be applied to the unselected word lineUnsel.WL3 adjacent thereto in the direction of the common source lineCSL as well as the unselected word line Unsel.WL4 not adjacent theretoin the direction of the common source line CSL.

The third pass voltage VPASS_READ3, applied to the unselected word lineUnsel.WL3 in the direction of the common source line CSL, may be changedin response to the bit line voltage VBL and continue to be input.

In general, the third pass voltage VPASS_READ3 satisfyingVPASS_READ1+gamma*VBL may be input, and gamma may have a value between−1.0 and +1.0.

Referring to FIG. 5F, a gate bias setup period may be set as illustratedin FIG. 5D. During a sensing bias setup period, the peripheral circuits120 to 160, shown in FIG. 1, may apply the precharge voltage VBL to thebit line BL when the selected word line Sel.WL and the unselected wordlines Unsel.WL1 and Unsel.WL2 adjacent thereto in the direction of thebit line BL are set to a floating state.

The peripheral circuits 120 to 160, shown in FIG. 1, may continue toapply the pass voltages VPASS_READ3 and VPASS_READ4 to the selected wordline Sel.WL and the unselected word lines Unsel.WL3 and Unsel.WL4 in thedirection of the common source line CSL.

Referring to FIG. 5G, during a gate bias setup period, when the passvoltage VPASS_READ is applied to the unselected word lines Unsel.WL,both the drain selection transistor and the source selection transistormay be turned on by applying the positive voltage to the selection linesDSL and SSL. During the sensing bias setup period, while the prechargevoltage VBL is applied to the bit line BL and the unselected word linesUnsel.WL to the floating state, the drain selection transistor and thesource selection transistor may be turned off by applying a groundvoltage to the selection lines DSL and SSL. Subsequently, during asensing period, while the precharge voltage VBL is applied to the bitline BL and the unselected word lines Unsel.WL are set to the floatingstate, the drain selection transistor and the source selectiontransistor may be turned on by applying the positive voltage to theselection lines DSL and SSL.

The unselected word lines Unsel.WL may be selectively floated by themethod described above with reference to FIGS. 5B to 5F. In addition,the pass voltage applied to the unselected word lines Unsel.WL may beset by the method described above with reference to FIGS. 5B to 5F.

As described above, during the gate bias setup period, when the passvoltage VPASS_READ is applied to the selected word lines Unsel.WL, aread speed may be improved by reducing the time it takes to prechargethe word lines by turning on all selection transistors. In addition,read stress caused by a read bias may be reduced by turning off allselection transistors during the sensing bias setup period.

Under the above-described conditions, when pass voltages are applied tounselected word lines, and a precharge voltage is applied to a bit linewhile a part or all of the unselected word lines are floated, anoperating current may be sufficiently ensured to improve data input andoutput characteristics.

FIG. 6 is a schematic block diagram of a memory system according to anembodiment of the present invention.

Referring to FIG. 6, a memory system 600 according to an embodiment ofthe present invention may include a non-volatile memory apparatus 620and a memory controller 610.

The non-volatile memory apparatus 620 may be composed of theabove-described semiconductor memory apparatus. The memory controller610 may be suitable for controlling the non-volatile memory apparatus620.

The memory system 600 having the above-described configuration may be amemory card or a solid state disk (SSD) in which the non-volatile memoryapparatus 620 and the memory controller 610 are combined. SRAM 611 mayfunction as an operation memory of a CPU 612. A host interface 613 mayinclude a data exchange protocol of a host being coupled to the memorysystem 600. An ECC 614 may detect and correct errors included in a dataread from the non-volatile memory apparatus 620. A memory interface 614may interface with the non-volatile memory apparatus 620. The CPU 612may perform the general control operation for data exchange of thememory controller 610.

Though not illustrated in FIG. 6, the memory system 600 may furtherinclude ROM (not illustrated) that stores code data to interface withthe host. In addition, the non-volatile memory apparatus 620 may be amulti-chip package composed of a plurality of flash memory chips. Thememory system 600 may be provided as a storage medium having highreliability and low error rate. A flash memory apparatus according to anembodiment of the present invention may be provided in a memory systemsuch as a semiconductor disk device (a solid state disk (SSD)) on whichresearch has been actively conducted. For example, when the memorysystem 600 is an SSD, the memory controller 110 may communicate with theoutside (e.g., a host) through one of the interface protocols includingUSB, MMC, PCI-E, SATA, PATA, SCSI, ESDI and IDE.

FIG. 7 is a schematic block diagram of a fusion memory apparatus or afusion memory system that performs a program operation according to theaforementioned various embodiments. For example, technical features ofthe present invention may be applied to a OneNand flash memory apparatus700 as the fusion memory apparatus.

The OneNand flash memory apparatus 700 may include a host interface(I/F) 710, a buffer RAM 720, a controller 730, a register 740 and a NANDflash cell array 750. The host interface 710 may be suitable forexchanging various types of information with a device through adifferent protocol. The buffer RAM 720 may have built-in codes fordriving the memory apparatus or temporarily store data. The controller730 may be suitable for controlling read and program operations andevery state in response to a control signal and a command that areexternally given. The register 740 may be suitable for storing dataincluding instructions, addresses and configurations defining a systemoperating environment in the memory apparatus. The NAND flash cell array750 may include operating circuits including non-volatile memory cellsand page buffers. In response to a write request from a host, theOneNAND flash memory apparatus 700 may program data in theaforementioned manner.

FIG. 8 is a schematic block diagram of a computing system including aflash memory apparatus 812 according to an embodiment of the presentinvention.

Referring to FIG. 8, a memory system 810 according to an embodiment ofthe present invention may include a flash memory 812 and a memorycontroller 811.

The flash memory 812 may be composed of the above-describedsemiconductor memory apparatus. The memory controller 811 may besuitable for controlling the flash memory 812.

A computing system 800 according to an embodiment of the presentinvention may include a microprocessor (CPU) 820, RAM 830, a userinterface 840, a modem 850, such as a baseband chipset, and a memorysystem 810 that are electrically coupled to a system bus 860. Inaddition, if the computing system 800 is a mobile device, then a batterymay be provided to apply operating voltages to the computing system 800.Though not shown in FIG. 8, the computing system 800 may further includeapplication chipsets, a Camera Image Processor (CIS), or mobile DRAM.The memory system 810 may form a Solid State Drive/Disk (SSD) that usesa non-volatile memory to store data. The memory system 810 may beprovided as a fusion flash memory (e.g., OneNAND flash memory).

A semiconductor memory apparatus according to an embodiment of thepresent invention may improve operating characteristics.

What is claimed is:
 1. A semiconductor memory apparatus, comprising: amemory block including memory cells coupled between a bit line and asource line and operating in response to voltages applied to word lines;and a peripheral circuit suitable for performing operations related todata input and output of the memory cells, wherein the peripheralcircuit is suitable for applying a pass voltage to a word line adjacentto a selected word line in a direction of the bit line and subsequentlyapplying a precharge voltage to the bit line when the word line adjacentto the selected word line is set to a floating state.
 2. Thesemiconductor memory apparatus of claim 1, wherein the peripheralcircuit is suitable for turning on a drain selection transistor coupledbetween the bit line and the memory cell when the pass voltage isapplied to the word line adjacent to the selected word line, and theperipheral circuit is suitable for setting a gate of the drain selectiontransistor to the floating state when the word line adjacent to theselected word line is set to the floating state.
 3. The semiconductormemory apparatus of claim 1, wherein the peripheral circuit is furtherconfigured to apply the precharge voltage to the bit line after the wordlines adjacent to the selected word line are floated.
 4. Thesemiconductor memory apparatus of claim 2, wherein the peripheralcircuit is further configured to apply a read voltage or the verifyvoltage to the selected word line when or after the precharge voltage isapplied to the bit line.
 5. The semiconductor memory apparatus of claim1, wherein the peripheral circuit is further configured to turn on adrain selection transistor between the bit line and the memory cellbefore the word lines adjacent to the selected word line are floated. 6.The semiconductor memory apparatus of claim 1, wherein the peripheralcircuit is further configured to float the word lines adjacent to theselected word line after a pass voltage is applied to the word lines. 7.The semiconductor memory apparatus of claim 6, wherein the peripheralcircuit is further configured to apply the precharge voltage to the bitline after the pass voltage is applied to the word lines.
 8. Thesemiconductor memory apparatus of claim 6, wherein the peripheralcircuit is further configured to turn on a drain selection transistorcoupled between the bit line and the memory cell when the pass voltageis applied to the word lines.
 9. The semiconductor memory apparatus ofclaim 1, wherein the peripheral circuit is further configured to apply aread voltage or a verify voltage to the selected word line when or afterthe word lines adjacent to the selected word line are floated.
 10. Thesemiconductor memory apparatus of claim 9, wherein the peripheralcircuit is further configured to apply the read voltage or the verifyvoltage after a pass voltage is applied to the selected word line. 11.The semiconductor memory apparatus of claim 9, wherein the peripheralcircuit is further configured to turn on a source selection transistorelectrically connecting the source line and the memory cell after theread voltage or the verify voltage is applied to the selected word line.12. The semiconductor memory apparatus of claim 1, wherein theperipheral circuit is further configured to turn on a source selectiontransistor electrically connecting the source line and the memory cellafter the word lines adjacent to the selected word line are floated. 13.The semiconductor memory apparatus of claim 1, wherein the peripheralcircuit is further configured to apply a first pass voltage to wordlines not adjacent to the selected word line and to apply a second passvoltage to the word lines adjacent to the selected word line before theword lines adjacent to the selected word line are set to the floatingstate.
 14. The semiconductor memory apparatus of claim 1, wherein theperipheral circuit is further configured to apply a first pass voltageto word lines not adjacent to the selected word line, to apply a secondpass voltage to a word line adjacent to the selected word line in onedirection and to apply a third pass voltage to a word line adjacent tothe selected word line in the other direction before the word linesadjacent to the selected word line are set to the floating state. 15.The semiconductor memory apparatus of claim 14, wherein the peripheralcircuit is further configured to set the word lines not adjacent to theselected word line in the one direction to the floating state when theword lines adjacent to the selected word line are set to the floatingstate.
 16. The semiconductor memory apparatus of claim 1, wherein theperipheral circuit is further configured to apply a first pass voltageto word lines not adjacent to the selected word line in one direction,to apply a second pass voltage to a word line adjacent to the selectedword line in the one direction, to apply a third pass voltage to a wordline adjacent to the selected word line in the other direction and toapply a fourth pass voltage to word lines not adjacent to the selectedword line in the other direction before the word lines adjacent to theselected word line are set to the floating state.
 17. The semiconductormemory apparatus of claim 16, wherein the peripheral circuit is furtherconfigured to set the word lines not adjacent to the selected word linein the one direction and the word lines not adjacent to the selectedword line in the other direction to the floating state when the wordlines adjacent to the selected word line are set to the floating state.18. The semiconductor memory apparatus of claim 1, wherein theperipheral circuit is further configured to set a gate of a drainselection transistor coupled between the bit line and the memory cell tothe floating state when the word lines adjacent to the selected wordline are set to the floating state.
 19. A semiconductor memoryapparatus, comprising: a memory block including memory cells operatingin response to voltages applied to word lines and selection transistorsoperating in response to voltages applied to selection lines between abit line and a source line; and a peripheral circuit suitable forperforming operations related to data input and output of the memorycells, wherein the peripheral circuit is suitable for turning on theselection transistors when a pass voltage is applied to unselected wordlines and turning off and subsequently turning on the selectiontransistors when the precharge voltage is applied to the bit line andthe unselected word lines are set to a floating state.